In recent years, studies are actively made with regard to a mass-storage ferroelectric-type nonvolatile semiconductor memory. A ferroelectric-type nonvolatile semiconductor memory (to be sometimes abbreviated as “nonvolatile memory” hereinafter) permits fast access and is nonvolatile, and it is small in size and consumes low-level electric power. Further, the ferroelectric-type nonvolatile semiconductor memory is highly impact-resistant, and it is expected to be used as a main memory in various electronic devices having file storage and resume functions, such as a portable computer, a cellular phone and a game machine, or to be used as a recording medium for recording voices and video images.
The above nonvolatile memory is a fast rewritable nonvolatile memory according to a method in which fast polarization inversion of a ferroelectric thin film and residual polarization thereof are used, and a change in an accumulated charge amount in a memory cell (capacitor member) having a ferroelectric layer is detected. In principle, the nonvolatile memory comprises the memory cell and a transistor for selection (transistor for switching). The memory cell comprises, for example, a lower electrode, an upper electrode and a ferroelectric layer interposed between them. Data is written into and read out from the above nonvolatile memory by application of a P-E hysteresis loop of a ferroelectric material shown in FIG. 27. That is, when an external electric field is applied to the ferroelectric layer and then removed, the ferroelectric layer exhibits residual polarization. The residual polarization comes to be +Pr when an external electric field in the plus direction is applied, and it comes to be −Pr when an external electric field in the minus direction is applied. In this case, a case where the residual polarization is in a +Pr state (see “D” in FIG. 27) is taken as “0”, and a case where the residual polarization is in a −Pr state (see “A” in FIG. 27) is taken as “1”.
For discriminating states of “1” and “0”, an external electric field, for example, in the plus direction is applied to the ferroelectric layer, whereby the polarization of the ferroelectric layer comes to be in a “C” state in FIG. 27. When the data is “0”, the polarization state of the ferroelectric layer changes from “D” to “C”. When the data is “1”, the polarization state of the ferroelectric layer changes from “A” to “C” through “B”. When the data is “0”, no polarization inversion takes place in the ferroelectric layer. When the data is “1”, polarization inversion takes place in the ferroelectric layer. As a result, there is caused a difference in the accumulated charge amount in the memory cell. The transistor for selection in a selected nonvolatile memory is turned on, whereby the accumulated charge is detected as a signal current. When the external electric field is changed to 0 after the data is read out, the polarization state of the ferroelectric layer comes into a “D” state in FIG. 27 both when the data is “0” and when the data is “1”. That is, when the data is read out, the data “1” is once destroyed when the data is “1”, therefore, an external electric field in the minus direction is applied, so that the polarization state is brought into “A” state through “D” and “E” to re-write data “1”.
The structure and the operation of a currently mainstream nonvolatile memory are proposed by S. Sheffiled et al in U.S. Pat. No. 4,873,664. The above nonvolatile memory is constituted of two nonvolatile memory cells as shown in an equivalent circuit diagram of FIG. 28. In FIG. 28, each nonvolatile memory is surrounded by a dotted line. Each nonvolatile memory is constituted, for example, of transistors for selection TR11 and TR12 and memory cells MC11 and MC12.
Concerning two-digit or three-digit subscripts, for example, a subscript “11” is a subscript that should be shown as “1,1”, and for example, a subscript “111” is a subscript that should be shown as “1,1,1”. For simplified showing, the subscripts are shown as two-digit or three-digit subscripts in some cases. Further, a subscript “M” is used to show, for example, all of a plurality of memory cells or plate lines, and a subscript “m” is used to show individuals, for example, of a plurality of the memory cells or the plate lines. A subscript “N” is used to show, for example, all of transistors for selection or sub-memory units, and a subscript “n” is used to show, for example, individuals of the transistors for selection or the sub-memory units.
Complement data is written into each memory cell, and the memory cells store 1 bit. In FIG. 28, symbol “WL” stands for a word line, symbol “BL” stands for a bit line, and symbol “PL” stands for a plate line. When one nonvolatile memory is taken, word line WL1 is connected to a word line decoder/driver WD. Bit lines BL1 and BL2 are connected to a sense amplifier SA. Further, plate line PL1 is connected to a plate line decoder/driver PD.
When stored data is read out in the thus-structured nonvolatile memory, the word line WL1 is selected, and further, the plate line PL1 is driven. In this case, complement data appears in a pair of the bit lines BL1 and BL2 as voltages (bit line voltages) from a pair of the memory cells MC11 and MC12 through the transistors for selection TR11 and TR12. The voltages (bit line voltages) in a pair of the bit lines BL1 and BL2 are detected with the sense amplifier SA.
One nonvolatile memory occupies a region surrounded by the word line WL1 and a pair of the bit lines BL1 and BL2. If the word lines and the bit lines are arranged at a smallest pitch, therefore, the smallest area that one nonvolatile memory can have is 8F2 when the minimum processable dimension is F. The thus-structured nonvolatile memory therefore has a smallest area of 8F2.
When it is attempted to increase the capacity of the above-structured nonvolatile memory, all that can be done relies on conversion of processable dimensions to finer dimensions. Further, two transistors for selection and two memory cells are required for constituting one nonvolatile memory. Furthermore, it is required to arrange the plate lines at the same pitch as that at which the word lines are arranged. It is therefore almost impossible to arrange nonvolatile memories at the minimum pitch, and in reality, the area that one nonvolatile memory occupies comes to be much larger than 8F2.
Moreover, it is also required to arrange the word line decoder/drivers WD and the plate line decoder/drivers PD at a pitch equivalent to a pitch at which the nonvolatile memories are arranged. In other words, two decoder/drivers are required for selecting one low-address. It is therefore difficult to layout peripheral circuits, and the area that the peripheral circuits occupy comes to be large.
One of means for decreasing the area of the nonvolatile memory is disclosed in JP-A-9-121032. As shown in an equivalent circuit diagram of FIG. 29, the nonvolatile memory disclosed in the above Publication comprises a plurality of memory cells MC1M (for example, M=4) ends of which are connected to one end of one transistor for selection TR1 in parallel, and a nonvolatile memory forming a pair with the above nonvolatile memory also comprises a plurality of memory cells MC2M ends of which are connected to one end of one transistor for selection TR2 in parallel. The other ends of the transistors for selection TR1 and TR2 are connected to bit lines BL1 and BL2, respectively. The bit lines BL1 and BL2 forming a pair are connected to a sense amplifier SA. Further, the other ends of the memory cells MC1m and MC2m (m=1, 2 . . . M) are connected to a plate line PLm, and the plate line PLm is connected to a plate line decoder/driver PD. Further, a word line WL is connected to a word line decoder/driver WD.
Complement data is stored in a pair of the memory cells MC1m and MC2m (m=1, 2 . . . M). For reading out the data stored, for example, in the memory cells MC1m and MC2m (wherein m is one of 1, 2, 3 and 4), the word line WL is selected, and in a state where a voltage of (½) Vcc is applied to the plate lines PLk (k≠m), the plate line PLm is driven. The above Vcc is, for example, a power source voltage. By the above procedure, the complement data appears in a pair of the bit lines BL1 and BL2 as voltages (bit line voltages) from a pair of the memory cells MC1m and MC2m through the transistors for selection TR1 and TR2. And, the sense amplifier SA detects the voltages (bit line voltages) in a pair of the bit lines BL1 and BL2.
A pair of the transistors for selection TR1 and TR2 in a pair of the nonvolatile memories occupy a region surrounded by the word line WL and a pair of the bit lines BL1 and BL2. If the word lines and the bit lines are arranged at a smallest pitch, therefore, a pair of the transistors for selection TR1 and TR2 in a pair of the nonvolatile memories have a minimum area of 8F2. Since, however, a pair of the transistors for selection TR1 and TR2 are shared by M sets of pairs of the memory cells MC1m and MC2m (m=1, 2 . . . M), the number of the transistors for selection TR1 and TR2 per bit can be decreased, and the layout of the word lines WL is moderate, so that the nonvolatile memory can be easily decreased in size. Further, with regard to peripheral circuits, M bits can be selected with one word line decoder/driver WD and M plate line decoder/drivers PD. When the above constitution is employed, therefore, the layout in which the cell area is close to 8F2 can be attained, and a chip size almost equivalent to a DRAM can be attained.
The method of writing data in the nonvolatile memory disclosed in JP-A-9-121032 will be explained below. The following explanation is based on an assumption that data is written into a pair of the memory cells MC11 and MC21, that data “1” is written into the memory cell MC11 and that data “0” is written into the memory cell MC21. FIG. 11 shows a waveform of an operation. In FIG. 11, parenthesized numerals correspond to numbers of steps to be explained below.
(1) In a standby state, the word line and all of the plate lines have 0 volt. Further, the bit lines BL1 and BL2 are equalized to have 0 volt. It is also assumed that data to be written is held in the sense amplifier SA.
(2) When writing of data is started, a high potential VBL-H (=Vcc) is applied to the bit line BL1, and a low potential VBL-L (=0 volt) is applied to the bit line BL2. The above Vcc refers to a power source voltage.
(3) Then, the potential of the word line WL is brought to a high level, thereby to bring the transistors for selection TR1 and TR2 into an ON-state. A high potential VPL-H (=Vcc) is also applied the selected plate line PL1, and an intermediate potential VPL-M [=(½)Vcc] is applied to a non-selected plate lines PLk (k=2, 3, 4). By the above procedures, in the memory cell MC21, the potential of the selected plate line PL1 is a high potential VPL-H and the potential of the bit line BL2 is a low potential VBL-L, so that data “0” is written.
(4) Then, the potential of the selected plate line PL1 is changed to a low potential VPL-L (=0 volt), whereby, in the memory cell MC11, the potential of the selected plate line PL1 is a low potential VPL-L and the potential of the bit line BL1 is a high potential VBL-H, so that data “1” is written.
When writing of data is finished, the potential of the word line WL is brought to a low level, thereby to bring the transistors for selection TR1 and TR2 to an OFF-state. Then, the bit line BL1 is discharged to a level of 0 volt, and the non-selected plate lines PLk (k=2, 3, 4) are discharged to a level of 0 volt.
In the above writing operation, (½) Vcc is applied to the non-selected plate lines PLk (=2, 3, 4). Therefore, a voltage of ±(½) Vcc is applied to each of the non-selected memory cells MC1k and MC2k (k=2, 3, 4). In some data stored in the non-selected memory cells MC1k and MC2k (k=2, 3, 4), therefore, an electric field may work on the ferroelectric layers of the memory cells constituting the non-selected memory cells MC1k and MC2k in the direction in which the polarization is inversed, and the data holding state may be deteriorated by disturbance. The disturbance refers to a phenomenon that an electric field works on the ferroelectric layer in the memory cell constituting the non-selected memory cell in the direction in which the polarization is inversed, that is, held data is deteriorated or destroyed.
As measures to be taken against the above disturbance, in the nonvolatile memory disclosed in JP-A-9-121032, the memory cells MC1m and MC2m in the memory unit composed of the memory cells MC1M and the memory cells MC2M are accessed from m=1 to m=M consecutively and collectively. By the above procedures, the number of disturbances that the memory cells MC1m and MC2m suffer is limited to (M−1) times. In this operation, data is written into the memory cells consecutively from the memory cells MC11 and MC21 in the first place to the memory cells MCM1 and MC2M in the M-th place without particularly external addressing. That is, data is written into the memory cells MC11 and MC21 located in the position of m=1, then, data is written into the memory cells MC12 and MC22 located in the position of m=2, and this operation is repeated until m=M is reached. In this manner, the number of disturbances that the memory cells MC1m and MC2m suffer is limited to (M−1) times. In reading-out of data and re-writing of data in the memory cells MC1m and MC2m, the memory cells MC1m and MC2m are similarly accessed consecutively and collectively from m=1 to m=M.
The method of decreasing the area of the nonvolatile memory, disclosed in JP-A-9-121032, is very effective. However, writing of data, reading-out of data and re-writing of data are consecutively started in the memory cells located in the first place. It is said that reading-out of data and re-writing of data in the memory cells MC1m and MC2m take a time period of approximately 100 nanoseconds. Therefore, reading-out and re-writing of data, for example, in memory cells MC18 and MC28 located in the eighth place take place approximately 0.8 microseconds after the reading-out and re-writing of data is started. There is therefore involved a problem that reading-out and re-writing of data in a desired memory cell take a time. Further, when writing of data is carried out, data are written into all of the memory cells constituting the memory unit. There is therefore involved a problem that writing of data in a desired memory cell takes a time. With an increase in the number of memory cells constituting the memory unit, the area efficiency improves, but accessing a memory cell comes to be slow on the other hand.
It is therefore an object of the present invention to provide a ferroelectric-type nonvolatile semiconductor memory that permits a prompt access to a desired memory cell while suppressing the influence of disturbance, and an operation method thereof.